1. Field of the Invention
The present invention relates to a semiconductor device of a CSP (Chip Size Package) structure and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a semiconductor device of a CSP structure, in which the chip size is substantially equal to the package size, has come to be employed for increasing the mounting density of the circuit substrate. FIG. 40 is a cross sectional view exemplifying the construction of a semiconductor device of a CSP structure, and FIG. 41 is a cross sectional view along the line V—V shown in FIG. 40 showing the construction of the semiconductor device excluding a conductor layer 5.
As shown in the drawings, the semiconductor device 10 comprises a plurality of connection pads 2 formed of aluminum electrodes or the like and formed on the front side (circuit side) of a semiconductor substrate 1. A passivation film 3 consisting of silicon oxide, silicon nitride or the like is formed on the side of the upper surfaces of the substrate 1 and the connection pads 2 in a manner to expose the central portion of each of the connection pads 2. Also, a circuit element-forming region DA is formed on the front surface of the semiconductor substrate 1 except the forming region of the connection pads 2, and circuit elements are formed in an integrated manner within the circuit element-forming region DA.
A protective film 4 is formed on the passivation film 3 in a manner to form an open portion in the central portion of each connection pad 2. For forming the protective film 4, the entire surface on the side of the circuit of the semiconductor substrate 1 is coated with, for example, a polyimide series resin material, followed by curing the coated resin material. Then, a resist patterning and a protective film patterning are applied by using an etching solution, followed by peeling off the resist film so as to form the protective film 4.
Conductive layers 5 each electrically connected to the connection pad 2 are formed on the protective film 4, a plurality of posts 6 for connection to the external circuit, which are columnar electrodes are formed in predetermined positions on the conductor layers 5. As described herein later, a metallizing treatment such as a solder printing is applied to the tip of the post 6 so as to form a metallized projecting edge surface 6a that is to be connected to a terminal (not shown) on the circuit substrate. Also, the post 6 is formed straight in a height of at least 50 μm and typically about 100 to 150 μm so as to absorb the stress generated by the difference in the thermal expansion coefficient between the semiconductor substrate 1 and the circuit substrate.
A sealing film 7 made of a resin material such as a polyimide resin or an epoxy resin is formed on that portion of the entire circuit surface of the semiconductor substrate 1 which is positioned between the adjacent posts 6. As described above, a native oxide film is removed from the projecting edge surface 6a of the post 6, followed by applying a metallizing treatment such as a solder printing to the projecting edge surface 6a so as to form a terminal portion for connection to the external circuit. Where the semiconductor device of the construction described above is mounted to a circuit substrate, the terminal portion of the post 6 for the connection to the external circuit is arranged to face the terminal of the circuit substrate and bonded by, for example, a soldering to the terminal of the circuit substrate so as to achieve the mounting of the semiconductor device to the circuit substrate.
For forming a transceiver chip equipped with a wireless I/F function such as Bluetooth, it is absolutely necessary for the semiconductor chip to be equipped with an RF functional elements such as a PLL circuit, a VCO circuit or a filter circuit. For realizing these RF functional elements, it is necessary to arrange various passive elements such as a capacitance element and an inductance element in the circuit element-forming region DA of the semiconductor substrate 1.
However, the formation of these passive elements necessitates a relatively large area, with the result that, if these passive elements are to be formed in the circuit element-forming region DA, the chip area is unavoidably increased. If the chip area is increased in the semiconductor device 10 of the CSP structure described above, various problems are generated. For example, it is impossible to increase the mounting density on the circuit substrate. Also, the number of chips that can be obtained from a single semiconductor wafer is decreased so as to lower the yield of manufacture and to increase the manufacturing cost.
Such being the situation, the various passive elements for realizing the RF functional elements are formed as discrete parts and mounted on the outside of the chip. However, it is difficult to decrease the size of the RF module with such a system.